1. Field of the Invention
The present invention relates to computer systems. More specifically, the invention relates to a cache memory and method of operating a cache memory in a computer system.
2. Description of the Related Art
A cache memory is a high-speed memory array which acts as a buffer between a CPU and a main memory of a computer system. A cache memory is effective because most software repeatedly executes the same instructions or manipulates data in the same spatial location in the memory. A cache memory increases effective memory speed by accessing slower main memory only once to fetch instructions or data with subsequent executions operating from the faster cache memory. A cache memory includes a data memory, a controller, and a directory.
The cache memory controls the CPU. If the cache memory includes a valid copy of data requested by the CPU during a CPU read cycle, then the cache allows the CPU to operate at the speed of the cache. If the cache does not contain a copy of the data, then the cache initiates a main memory read cycle, copies the data supplied by the main memory which the main memory indicates is valid using a ready signal, and allows the CPU to continue operating. Data applied to the CPU is routed by the cache controller either from the cache for the case of a cache hit or from buffers that isolate the main memory from the CPU for a cache miss. The cache hit results in no wait states. For the cache miss, the cache controller disables a memory ready signal so that the CPU inserts wait states. The cache memory performs this control function by intercepting all signals from the CPU, including input signals and output signals, thereby isolating the CPU from other devices.
Generally, when a cache miss occurs, not only the requested data bytes but also a complete cache line is read from the main memory into the cache memory in an operation called a cache line fill. A cache line typically includes 16 or 32 bytes. The cache line fill replaces a line in the cache. Data that is changed while in the cache is written to memory prior to replacement. One technique for writing changed cache data to memory is a write-through technique in which a write operation of the CPU causes a data transfer to main memory both for cache hits and cache misses. The write-through technique advantageously ensures consistency of the main memory, if only for single-processor systems. The write-through technique disadvantageously causes wait states.
An alternative technique for writing changed cache data to memory is a write-back cache technique in which all write operations are collected and the main memory is only updated upon receipt of an explicit update command or inquiry. One example of such a command is a software "write-back and invalidate data cache" (WBINVD) instruction. Another example of such a command is a hardware FLUSH signal which occurs implicitly as the result of a cache miss. The disadvantage of the write-back cache is that the exchange of cache lines has a longer duration because data must be written into memory before new data is read into the CPU.
A further alternative technique is a write-allocate technique in which a the cache controller implements a write-allocate strategy by filling the cache space for a cache line with the data for the address to be written. Usually, the data is first written through to the memory. The cache controller then reads the applicable cache line with the entry to be updated into the cache. The data is written through so that the CPU can restart program execution. The cache controller independently performs the write-allocate in parallel with the CPU operation.
With the advent of multimedia computer systems, a wide variety of data flows, data volumes and data characteristics are handled by caches. Multimedia computers access data in the forms of video data flows, audio data flows, video frames and the like, in addition to conventional handling of data and instructions. Caching characteristics of the different data flows are substantially different. For example, video data may flow through a cache memory while undergoing recursive processing in which the same data is processed periodically. The video data quickly is replaced due to the large volumes of data that is processed. The same data then must be brought back into the cache for recursive processing. This processes constantly repeats causing considerable thrashing of the cache memory.
Similarly, audio data typically involves smaller data volumes but is most efficiently handled using cache strategies that are different from strategies used for handling video data, conventional data or operating instructions.
What is needed is an apparatus and method for controlling the caching of different types of data which effectively considers the characteristics of the various data types.